`timescale 1ns/1ns

module mdio_bit_shift_tb;

	reg mdc;
	reg rst_n;
	reg start;
	reg if_read;
	reg [4:0] phy_addr;
	reg [4:0] reg_addr;
	reg [15:0] wrdata;
	wire mdio;
	wire done;
	wire [15:0] rddata;

	mdio_bit_shift	mdio_bit_shift_inst(
		.mdc				(mdc		),	//时钟接口
		.rst_n			(rst_n	),			//模块复位，低电平有效
		.start			(start	),			//开始传输标志
		.if_read			(if_read	),	//读写方向控制 1:读，0:写
		.phy_addr		(phy_addr),			//5位的phy地址输入信号，最高2位为0
		.reg_addr		(reg_addr),			//5位的reg地址输入信号
		.wrdata			(wrdata	),			//要写入phy寄存器的16位数据
		.mdio				(mdio		),	//数据接口
		.done				(done		),	//操作完成标志
		.rddata			(rddata	)			//从phy寄存器读出的16位数据		
	);
	//模拟上拉
	pullup PUP(mdio);	
	initial mdc = 1;
	always #10 mdc = ~mdc;
	
	initial begin
	rst_n = 0;
	if_read = 0;//写
	phy_addr = 5'b00000;
	reg_addr = 5'b00000;
	wrdata = 16'd0;
	start = 0;
	#201;
	rst_n = 1;
	if_read = 0;
	phy_addr = 5'b00001;
	reg_addr = 5'b00000;
	wrdata = 16'h2100;
	@(posedge mdc);
	start = 1;
	@(posedge done);
	#200;
	//$stop;
	
	end

endmodule 